This article proposes a constant current regulation design for primary-side controlled flyback converter. The regulation circuit consists of two parts: an OSC circuit and an adaptive primary side peak current threshold compensation circuit. The OSC circuit generates a switching cycle signal with a fixed ratio to the demagnetization time, and the adaptive primary side peak current threshold compensation circuit. To verify the feasibility and accuracy of the proposed constant current regulation design, the designed chip was fabricated and tested. Under 12 V/1.9 A configuration, the test results showed that the line regulation and load regulation of the output current can achieve within ±1.7% and ±0.15%, respectively.

A pulse stretch interpolator used in low-cost and low-power CMOS time-to-digital converter (TDC) is proposed in this paper. The reference clock frequency of the TDC is 6.4 MHz and the range is 5120 us. The chip size is 0.5 mm × 0.5 mm as fabricated in the TSMC 180 nm CMOS process. The time resolution can be realized as 10 ps and the power consumption is 1.92 mW. The time period of an input is divided into two parts. The first step of coarse quantization uses a clock to quantize an integer number of clock cycles. The second step of fine quantization is to stretch the pulse width of less than one clock cycle after coarse quantization. The pulse stretch interpolator charges and discharges the capacitor under narrow input pulse control in order to expand the narrow pulse. In this way, TDC achieves higher resolution with low power consumption. The pulse stretch interpolator’s resolution is 1.55 ps in all corners.

Latch-based resilient circuits significantly increases the area overhead to address short-path (SP) issues. This work presents a low-overhead resilient circuit with partial two-phase latch, which selectively inserts negative phase latches to resolve SP issues and reduces the number of insertion points. Furthermore, the monitoring paths reduction method is also proposed by leveraging the time-borrowing capability of latches. The proposed method is implemented on a RISC-V processor, achieving a performance enhancement of up to 73.7% and a power consumption reduction of up to 33%, with only a 6.5% area penalty.

This paper presents on the design, fabrication and test of a Schottky diode based mixer driving by a frequency doubler for solid-state receiver front-ends in the 380 GHz range. The 380 GHz sub-harmonic mixer has fabricated with the GaAs membrane process on a 3 μm-thick substrate suspended in a waveguide with metal beamleads, and exhibited an impressive double-side-band conversion loss of less than 10 dB in 1-23 GHz IF band with the optimal conversion loss of merely 6.4 dB. The 190 GHz frequency doubler based on Schottky diodes is the key in the local oscillator source and sufficiently pumps the mixer with 2~5 mW of input power.

This paper proposes a distributed secondary control strategy for heterogeneous battery energy storage systems (BESSs) in islanded microgrids, without requiring power measurements. The method uses local State-of-Charge (SoC) information to achieve energy balancing and proportional active power sharing by introducing distributed filters. Frequency and voltage regulation are also accomplished using local frequency and voltage information. The system stability under the proposed control strategy is rigorously proved based on the Lyapunov function method. Simulation is performed in the MATLAB/Simulink platform to verify the effectiveness of the proposed control method.

This letter proposes a novel design method for a resistive-resistive series of continuous modes (Res-Res SCMs) power amplifier (PA), which can extend the bandwidth of the SCMs PAs. With a waveform engineering method, we introduce the resistive part to the purely reactive second harmonic load of SCMs to overcome one-octave bandwidth limitation of traditional continuous PAs. The limitation is due to the inability to overlap between low-band and high-order harmonics and high-band fundamental waves. An ultra-wideband PA module across 0.4-3.1 GHz (154.3% bandwidth) is fabricated using a 10 W GaN HEMT device. The experimental results show a drain efficiency of 63%-81.7% can be achieved with a saturated output power of 38.6-42.3 dBm at 0.4-3.1 GHz.

This pretreating and decoding circuit is characterized by high speed and low area. This letter presents the shortest subsequence extraction algorithm as well as redefined and simplified methodology for character detection within single stage, eliminating redundant combinatorial logic and function block. Parallel 8B/10B decoder with mixed structure of decoding and disparity check is also proposed effectively. The circuit, acting as a significant role in JESD204B controller for Gigabit transmission, has been implemented and verified on Xilinx VC707 development kit. This design can achieve lane rate for up to 18.3 Gbps, with increase in frequency by 31% and decrease in area by 12% compared with typical architecture and the optimization of the key components is also greatly remarkable.

This paper discusses the complete absorption of microwaves by conductive plates and its application in heating technology. Numerical calculations were conducted to determine the conditions for complete absorption of 2.45 GHz microwaves propagating through a rectangular waveguide tube with an inner dimension of 5.5×10.9 cm². Based on the calculated results, we developed a resonating absorber with a three-layered structure of single-crystalline silicon (c-Si) which consisted of a 0.7-cm-thick semi-insulating c-Si substrate (DP) with a resistivity over 1000 Ωcm, a 0.49-cm-thick c-Si substrate (CP1) with 19-22 Ωcm, and a 0.05-cm-thick c-Si substrate (CP2) with 0.001 Ωcm or less. The absorber achieved complete microwave absorption with a measurement accuracy of 2%. Complete absorption was again observed when a half-wavelength (λ/2)-long air gap was introduced between the DP and CP1 layers. A radiation thermometer detected a temperature increase of 75.5 K in CP2 under 500 W microwave irradiation for 10 s, which was higher than the 43 K increase observed without the air gap. This demonstrates that the λ/2-air gap effectively provides thermal isolation between the DP and CP1 layers.

In zoom analog-to-digital converters (ADCs), due to the dynamic updating and scaling of fine reference voltages by coarse SAR ADC, traditional noise coupling technique cannot be directly applied to fine ΔΣ modulator, which may lead to modulator overload and a sharp decline in the signal-to-noise distortion ratio (SNDR). To address this issue, this article proposes a noise-coupled technique specifically designed for zoom ADCs. It establishes a mathematical model and determines the appropriate feedback voltage based on coarse quantization and the over-ranging factor, ultimately enhancing SNDR and energy efficiency. The zoom ADC is designed using a 180 nm CMOS process and incorporates two integrators to achieve 3^rd-order noise-shaping capability (60 dB/dec). It achieves an SNDR of 105.7 dB at a sampling frequency of 256 kHz and an oversampling rate of 128, with a power consumption of only 90.25 μW. The SNDR-based Schreier figure-of-merit (FoMs) is 176.1 dB, indicating competitive performance in terms of high resolution and energy efficiency.